This invention relates generally to the conversion of amorphous or polycrystalline semiconductor materials to substantially single crystal semiconductor material by a process known as zone-melting recrystallization.
From transistors to very large scale integration of complex circuitry on a single chip, the field of solid state electronics has been built largely upon the abundant non-metallic element silicon. Large diameter single crystal boules of silicon are sliced into wafers on which dopants, insulators and conductors are applied using a variety of processes. Over the past few years, a major effort has been devoted to developing a new silicon-based technology involvinq the preparation of very thin films of pure single crystal silicon on the the order of one-half micron thick, compared to the one-half millimeter thickness of typical silicon wafers. This emerging technology is called silicon-on-insulator (SOI) technology because the thin silicon (sic) film is supported by an insulating substrate. An efficient, reliable and economical process for producing thin film single crystal silicon has eluded researchers until now.
In comparison to device performance in bulk silicon, SOI promises significant advantages:
(1) improved speed performance in discrete devices and circuits resulting from reduced parasitic capacitance;
(2) simplified device isolation and design layout, yielding potentially higher packing densities; and
(3) radiation hard circuits for space and nuclear application.
In addition, new SOI technologies may also be utilized for three-dimensional integration of circuits.
At present, there is one relatively mature SOI technology, silicon-on sapphire (SOS). However, the commercial utilization of SOS has been severely limited by its high cost, relatively poor crystalline quality, and difficulty in handling and processing in comparison to bulk Si.
Recently, a new SOI technology called zone-melting recrystallization (ZMR) based on standard silicon wafers rather than sapphire crystals has exhibited the potential for displacing SOS and for utilization on a much larger scale by the semiconductor industry.
In known ZMR techniques, SOI is produced by recrystallizing a fine-grained Si film on an insulating substrate. A typical sample structure consists of a silicon wafer coated with a 1-micron, thermally grown SiO.sub.2 insulating layer, a half micron polycrystalline silicon (poly-Si) layer formed by low pressure chemical vapor deposition (LPVCD), capped by a 2-micron layer of CVD SiO.sub.2. The last layer forms a cover to encapsulate the polysilicon film constraining it while the film is being recrystallized.
The ZMR technique for SOI is described in a paper entitled "Zone Melting Recrystallization of Silicon Film With a Movable Strip Heater Oven" by Geis et al., J. Electrochem. Soc. Solid State Science and Technology, Vol., 129, p. 2812 (1982).
The sample is placed on a lower graphite strip and heated to a base temperature of 1100-1300.degree. in an argon gas ambient. Silicon has a melting point of about 1410.degree. C.; SiO.sub.2 has a higher melting point, about 1710.degree. C. Additional heat in the form of radiant energy is typically provided by a movable upper graphite strip heater which produces localized heating of the sample along a strip to a temperature between the two melting points. The upper heater scans the molten silicon zone across the sample leaving behind a recrystallized monocrystalline SOI film beneath the SiO.sub.2 cap.
The development of ZMR, however, has been frustrated by processing problems. The interface between the molten silicon and adjacent silicon dioxide layers gives rise to the so-called silicon beading phenomenon during ZMR which can fracture the SiO.sub.2 cap and lead to defects in the crystalline structure of the silicon. A solution to this problem is the subject of the above-referenced U.S. application Ser. No. 805,117.
A second obstacle to the commercial utilization of ZMR has been the presence of excessive edge defects and warping which result from heat buildup about the periphery of the wafer during processing. These defects require post-ZMR processing to both improve the cosmetic appearance and prepare the crystal for automated semiconductor processing. These problems are addressed by the patent application U.S. Ser. No. 238,311.
Yet another problem encountered in the ZMR method involves the presence of low angle grain boundaries or subboundaries in processed wafers which interrupt the crystalline structure in the silicon film and thereby reduce utility of the film in electronic applications.
Major ZMR research in past few years has been focused on eliminating these subboundaries. Recently, elimination of such defects was realized in one micron (1 um) Si SOI materials using low moveable strip heater power and velocity conditions. The precision and accuracy of the various experimental parameters required to produce this subboundary-free material was so high, however, that it was very difficult to practice. Furthermore, the range of acceptable parameters becomes even more restrictive in the manufacture of technologically and commercially more important half micron (0.5 um) SOI wafers.